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s3c7031/7032 product overview 1- 1 1 product overview over view the s3c7031/7032 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core. with comparator inputs, high-current led direct-drive pins, serial i/o interface, and a versatile 8-bit timer/counter, the s3c7031/7032 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. up to 15 pins of the 20-pin dip or 20-pin sop package can be dedicated to i/o. pull-up resistors are assignable to all of the pins by software. four vectored interrupts provide fast response to internal and external events. in addition, the s3c7031/7032 's advanced cmos technology provides for very low power consumption and a wide operating voltage range . development support the samsung microcontroller development system, smds, provides you with a complete pc-based development environment for ks57-series microcontrollers that is powerful, reliable, and portable. in addition to its easy to use window-oriented program development structure, the smds toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. the samsung generalized assembler (sama) has been designed specifically for the smds environment and accepts assembly language sources in a variety of microprocessor formats. sama generates industry-standard object files that also contain program control data for smds compatibility.
product overview s3c7031/7032 1- 2 features memory ? 1024 8-bit program memory (s3c7031) (rom) ? 2048 8-bit program memory (S3C7032) (rom) ? 128 4-bit data memory (s3c7031) (ram) ? 256 4-bit data memory (S3C7032) (ram) i/o pins ? up to 15 pins for 20-dip and 20-sop package comparator inputs ? 4-channel mode internal reference: 4-bit resolution ? 3-channel mode external reference 8-bit basic timer ? programmable interval timer 8-bit timer/counter ? programmable interval timer ? external event counter function ? timer clock output to tio pin watch timer ? time interval generation: 0.5 s, 3.9 ms at 4.19 mhz ? four frequency outputs to buz pin bit sequential carrier ? 16-bit serial data transfer in arbitrary format 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive-only mode ? lsb-first or msb-first transmission selectable ? internal or external clock source interrupts ? one external interrupt vector ? three internal interrupt vectors ? two quasi-interrupts memory-mapped i/o structure two power-down modes ? idle mode: only the cpu clock stops ? stop mode: main system clock stops on-chip crystal, ceramic, or rc oscillator ? crystal/ceramic: 4.19 mhz (typical) ? rc: 1 mhz (typical) ? cpu clock divider circuit (by 4, 8, or 64) frequency outputs ? eight frequency outputs to the clo pin instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (5 v), 4 s at 1 mhz (2.7 v) operating temperature: ? ? 40 c to 85 c operating voltage range: ? 2.7 v to 6.0 v package type: ? 20-dip, 20-sop
s3c7031/7032 product overview 1- 3 block diagram program status word flags arithmetic and logic unit instruction decoder internal interrupts reset 8-bit timer/ counter interrupt control block stack pointer clock program memory (1) data memory (2) comparator i/o port 1 p0.0/ ks0/cin0 p0.1/ks1/cin1 p0.2/ks2/cin2 p0.3/ks3/cin3 i/o port 3 p2.0 - p2.3 p3.0/ sck p3.1/so p3.2/si p3.3/buz i/o port 2 serial i/o port x out x in program counter basic timer watch timer i/o port 0 p0.0/ clo p0.1/tio p0.2/int1 notes: 1. program memory is 1-kbyte (s3c7031) and 2-kbyte (S3C7032). 2. data memory is 128 x 4bit (s3c7031) and 256 x 4bit (S3C7032). figure 1 -1 . s3c7031/7032 block diagram
product overview s3c7031/7032 1- 4 pin assignments p0.0/clo p0.1/tio p0.2/int1 p0.0/ks0/cin0 p0.1/ks1/cin1 p0.2/ks2/cin2 p0.3/ks3/cin3 x out x in v ss v dd p3.3/buz p3.1/so p3.2/si p3.0/ sck p2.3 p2.2 p2.1 p2.0 reset 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ks57c7031/ ks57c7032 (top view) note: pin assignments are identical for the 20-pin dip and sop package. figure 1 -2 . s3c7031/7032 pin assignment diagram (20-pin dip/sop package) pin descriptions table 1 - 1. s3c7031/7032 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 i/o 3-bit i/o port. 1-bit or 3-bit read/write and test is possible. pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 1 2 3 clo tio int1 p1.0 p1.1 p1.2 p1.3 i/o same as port 0 except that port 1 is a 4-bit i/o port. 4 5 6 7 ks0/cin0 ks1/cin1 ks2/cin2 ks3/cin3
s3c7031/7032 product overview 1- 5 table 1 - 1. s3c7031/7032 pin descriptions (continued) pin name pin type description number share pin p2.0 - p2.3 p3.0 p3.1 p3.2 p3.3 i/o 4-bit i/o port. 1-bit, 4-bit or 8-bit read/write and test is possible. pins are individually configurable as input or output. pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. ports are software configurable as n -channel open-drain outputs or push-pull output by software. ports 2 and 3 can be paired to enable 8-bit data transfer. 12 - 15 16 17 18 19 ? - sck so si buz clo i/o eight frequency outputs 1 p0.0 tio i/o external clock input or timer clock output 2 p0.1 int1 i/o external interrupts with rising or falling edge detection 3 p0.2 ks0 - ks3 i/o quasi-interrupts with falling edge detection 4 - 7 p1.0 - p1.3 cin0 - cin3 i/o 4-channel comparator input. cin0 - cin2: comparator input only. cin3: comparator input or external reference input 4 -7 p1.0 - p1.3 sck i/o serial interface clock signal 16 p3.0 so i/o serial data output 17 p3.1 si i/o serial data input 18 p3.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at 4.19 mhz for buzzer sound 19 p3.3 x in , x out ? - crystal, ceramic, or rc signal for system clock 9, 8 ? - reset i reset signal 11 ? - v dd ? - power supply 20 ? - v ss ? - ground 10 ? - table 1 - 2. overview of s3c7031/7032 pin data pin numbers pin names share pins i/o type reset value circuit type 1 - 3 p0.0 - p0.2 clo, tio, int1 i/o input 2 4 - 7 p1.0 - p1.3 ks0/cin0 - ks3/cin3 i/o input 4 12-5 p2.0 - p2.3 ? i/o input 3 16 - 19 p3.0 - p3.3 sck , so, si, buz i/o input 3 11 reset ? - i ? - 1 20, 10 v dd , v ss ? - ? - ? - ? - 9, 8 x in , x out ? - ? - ? - ? -
product overview s3c7031/7032 1- 6 pin circuit diagrams schmitt trigger in figure 1 -3 . pin circuit type 1 schmit trigger typical 50 k w (v dd = 5v) pull-up registor v dd pull-up enable i/o v dd output disable data vss figure 1 -4 . pin circuit type 2
s3c7031/7032 product overview 1- 7 schmit trigger typical 50 k w (v dd =5v) pull-up registor v dd pull-up enable i/o v dd output disable data vss open-drain figure 1 -5 . pin circuit type 3
product overview s3c7031/7032 1- 8 schmit trigger typical 50 k w (v dd =5v) pull-up registor v dd pull-up enable i/o v dd output disable data vss open-drain + in intk (quasi) (digital) ref (p1.3 only) in (analog) comparator ref digital or analog selectable by software p-ch figure 1 -6 . pin circuit type 4
s3c7031/7032 electrical data 14 - 1 14 electrical data overview in this section, information on s3c7031/7032 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? oscillators characteristics ? i/o capacitance ? comparator electrical characteristics ? a.c. electrical characteristics ? operating voltage range oscillation characteristics ? system clock oscillator frequencies and stabilization time stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c7031/7032 14- 2 miscellaneous timing waveforms ? clock timing measurement at x in ? tio timing ? input timing for reset ? input timing for external interrupts and quasi-interrupts ? serial data transfer timing characteristic curves ? i dd vs frequency ? i dd vs v dd ? i ol vs v ol (p0.0) ? i ol vs v ol (p1.1) ? i ol vs v ol (p2.0) ? i oh vs v oh (p0.0) ? i oh vs v oh (p1.1)
s3c7031/7032 electrical data 14 - 3 table 14 - 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? - 0.3 to + 7.0 v input voltage v i all i/o ports - 0.3 to v dd + 0.3 v output voltage v o ? - 0.3 to v dd + 0.3 v output current high i oh one i/o port active - 5 ma all i/o ports active - 15 output current low i ol one i/o port active 25 ma all i/o port, total 100 operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c table 14 - 2. d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units input high voltage v ih 1 ports 0, 1, 2, 3, reset 0.7 v dd ? v dd v v ih 2 x in , x out v dd - 0.5 ? v dd input low voltage v il 1 ports 0, 1, 2, 3, reset ? ? 0.3 v dd v v il 2 x in , x out 0.4 output high voltage v oh 1 v dd = 4.5 v to 6.0 v i oh = - 3 ma ports 0, 1, 2, 3 except p0.0 v dd - 1.0 v dd - 0.4 ? v v dd = 4.5 v to 6.0 v i oh = - 6 ma ports 0, 1, 2, 3 except p0.0 v dd - 2.0 v dd - 0.9 ? v oh 2 v dd = 4.5 v to 6.0 v i oh = - 10 ma p0.0 v dd - 2.0 ? ? output low voltage v ol 1 v dd = 4.5 v to 6.0 v i ol = 25 ma ports 0, 1, 2, 3 except p0.0 ? 1.4 2.0 v v ol 2 v dd = 4.5 v to 6.0 v i ol = 50 ma p0.0 ? 1.6 2.0 v
electrical data s3c7031/7032 14- 4 table 14 - 2. d.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units input high leakage current i lih 1 v in = v dd all input pins except i lih 2 ? ? 3 m a i lih 2 v in = v dd x in , x out 15 20 input low leakage current i lil 1 v in = 0 v all input pins except i lil 2 ? ? - 3 m a i lil 2 v in = 0 v x in , x out -15 - 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? - 3 m a pull- up resistor r l v in = 0 v; v dd = 5 v - 10 % ports 0, 1, 2, 3 15 50 80 k w v in = 0 v; v dd = 3 v - 10 % ports 0, 1, 2, 3 30 100 200 supply current (2) i dd 1 v dd = 5 v 10 % (2) 4.19 mhz crystal oscillator c1 = c2 = 22 pf ? 1.7 8.0 ma v dd = 3 v 10 % (3) 4.19 mhz crystal oscillator c1 = c2 = 22 pf 0.6 1.2 i dd 2 idle mode; v dd = 5 v 10 % 4.19 mhz crystal oscillator c1 = c2 = 22 pf ? 0.5 1.8 ma idle mode; v dd = 3 v 10 % 4.19 mhz crystal oscillator c1 = c2 = 22 pf 0.2 1.0 i dd 3 stop mode v dd = 5 v - 10 % 0.2 5 m a stop mode v dd = 3 v - 10 % 0.1 3 notes: 1. d.c. electrical values for supply current (i dd 1 to i dd 3) do not include current drawn through internal pull-up resistors. 2. for high-speed controller operation, set the pcon register to 0011b. 3. for low-speed controller operatio n, set the pcon register to 0000b.
s3c7031/7032 electrical data 14 - 5 table 14 - 3. oscillators characteristics (t a = - 40 c to + 85 c, v dd = 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 4.5 mhz stabilization time (2) after v dd reaches the minimum level of its vari able range ? ? 4 ms crystal oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 4.19 4.5 mhz stabilization time (2) v dd = 2.7 v to 4.5 v ? ? 30 ms v dd = 4.5 v to 6.0 v ? ? 10 external clock x in x out x in input frequency (1) ? 0.4 ? 4.5 mhz x in input high and low level width (t xh , t xl ) ? 111 ? 1250 ns rc oscillator x in x out r frequency v dd = 5 v 0.6 1 2.3 mhz v dd = 3 v 0.4 0.8 1.5 notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c7031/7032 14- 6 table 14 - 4. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 14 - 5. comparator electrical characteristics (t a = - 40 c to + 85 c, v dd = 4.0 v to 6.0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy internal reference v cin 1 ? ? ? - 150 mv external reference v cin 2 ? ? ? - 50 input leakage current i cin , i ref ? - 3 ? 3 m a
s3c7031/7032 electrical data 14 - 7 table 14 - 6. a.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 4.5 v to 6.0 v 0.95 ? 64 s v dd = 2.7 v to 4.5 v 3.8 tio input frequency f ti v dd = 4.5 v to 6.0 v 0 ? 1 mhz v dd = 2.7 v to 4.5 v 275 khz tio input high, low width t tih , t til v dd = 4.5 v to 6.0 v 0.48 ? ? s v dd = 2.7 v to 4.5 v 1.8 sck cycle time t kcy v dd = 4.5 v to 6.0 v; input 800 ? ? ns v dd = 4.5 v to 6.0 v; output 950 v dd = 2.7 v to 4.5 v; input 3200 v dd = 2.7 v to 4.5 v; output 3800 sck high, low width t kh , t kl v dd = 4.5 v to 6.0 v; input 400 ? ? ns v dd = 4.5 v to 6.0 v; output t kcy /2 - 50 v dd = 2.7 v to 4.5 v; input 1600 v dd = 2.7 v to 4.5 v; output t kcy / 2 - 50 si setup time to sck high t sik input 100 ? ? ns output 150 si hold time to sck high t ksi input 400 ? ? ns output 400 output delay for sck to so t kso v dd = 4.5 v to 6.0 v; input ? ? 300 ns v dd = 4.5 v to 6.0 v; output 250 v dd = 2.7 v to 4.5 v; input 1000 v dd = 2.7 v to 4.5 v; output 1000 interrupt input high, low width t inth , t intl int1, ks0 - ks3 10 ? ? s reset input low width t rsl input 10 ? ? s
electrical data s3c7031/7032 14- 8 1 2 3 4 5 6 7 15.6khz 250khz 500khz 1.0475mhz cpu clock supply voltage (v) cpu clock = 1/n x oscillator frequency (n =4, 8 or 64) 750khz 1.00mhz figure 14 -1 . standard operating voltage range table 14 - 7. ram data retention supply voltage in stop mode (t a = - 40 c to + 85 c) parameter symbol condition min typ max units data retention supply v oltage v dddr ? 2.0 ? 6.0 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillation stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c7031/7032 electrical data 14 - 9 timing waveforms data retention mode ~ ~ ~ v dddr execution of stop instrction v dd operating mode idle mode ~ stop mode internal reset operation reset t srel t wait figure 14-2.stop mode release timing when initiated by reset reset data retention mode ~ ~ ~ v dddr execution of stop instrction v dd ~ normal mode idle mode t srel t wait power - down mode terminating signal (interrupt request) stop mode figure 14-3. stop mode release timing when initiated by interrupt request
electrical data s3c7031/7032 14- 10 measurement points 0.3 v dd 0.7 v dd 0.7 v dd 0.3 v dd figure 14-4. a.c. timing measure points (except for x in ) x in v dd - 0.5v 0.4 v t xl t xh 1/fx figure 14 -5. clock timing measurement at x in tio 0.7 v dd 0.3 v dd t til t tih 1/f tcl figure 14 -6 . tio timing
s3c7031/7032 electrical data 14 - 11 reset 0.3 v dd t rsl figure 14 -7. input timing for reset reset signal int1 ks0 to ks3 0.3 v dd 0.7 v dd t inth t intl figure 14 -8 . input timing for external interrupts
electrical data s3c7031/7032 14- 12 output data t kso sck so si 0.3 v dd input data 0.7 v dd t kso t kis 0.3 v dd 0.7 v dd t kl t kh t kcy figure 14- 9 . serial data transfer timing
s3c7031/7032 electrical data 14 - 13 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. v ol (v) 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 70 63 54 49 42 35 21 28 14 7 v dd = 4.5v v dd = 6.0v i ol (ma) figure 14-10. i ol vs. v ol (port 0,1,2,3)
electrical data s3c7031/7032 14- 14 v ol (v) 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 100 90 80 70 60 50 30 40 20 10 i ol (ma) v dd = 4.5v v dd = 6.0v figure 14-11. i ol vs. v ol (port 0.0) v ol (v) 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 i ol (ma) v dd = 6.0v -30.0 -27.0 -24.0 -21.0 -18.0 -15.0 -9.0 -12.0 -6.0 -3.0 v dd = 4.5v figure 14-12. i oh vs. v oh (port 0,1,2,3except p0.0)
s3c7031/7032 electrical data 14 - 15 3.0 0 v dd (v) 2.5 2 1.5 1 0.5 3.0 0 4.0 5.0 6.0 i dd 1 (/4) i dd 2 i dd (ma) ~ ~ figure 14-13. i dd vs. v dd 0 fx (mhz) 2.5 2 1.5 1 0.5 3.0 0 4.0 5.0 1.0 i dd 1(ma) v dd = 5.5v(/4) 2.0 figure 14-14. i dd vs. frequency
s3c7031/7032 mechanical data 15- 1 15 mechanical data this section contains the following information about the device package: ? a 20-pin dip package is available for s3c7031/7032 . ? a 20-pin sop package is available for s3c7031/7032 . 20-dip-300a #20 #11 #10 #1 7.62 2.54 (1.77) 26.40 0.20 0.46 0.10 1.52 0.10 3.30 0.30 3.52 0.20 0.51 min 5.08 max 0-15 0.25 + 0.10 0.05 - 6.40 0.20 note: dimensions are in millimeters figure 15 - 1. 20-pin dip-300a package dimensions
mechanical data s3c7031/7032 15- 2 20-sop-375 #1 #10 #11 #20 9.53 2.30 0.10 2.50 max 0-8 (0.66) 10.30 0.30 12.74 0.20 0.05 min 1.27 0.85 0.20 7.50 0.20 note: dimensions are in millimeters 0.203 + 0.10 0.05 - 0.40 + 0.10 0.05 - figure 15 -2 . 20-pin sop-375 package dimensions

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